I’m a third-year PhD student at IIT Madras mentored by Prof. Pratyush Kumar and Prof.V. Kamakoti from IIT Madras and Prof. Anand Raghunathan from Purdue University.
My research broadly addresses the problem of improving the resource efficiency of systems running Deep Learning (DL) applications. This involves building efficient hardware for compute-intensive DL applications as well as making efficient use of existing hardware by performing hardware-aware algorithmic modifications to key kernels in Deep Neural Networks such as convolutions.
Whenever I find time, I also actively work on micro-architectural security - specifically on side-channel attacks and defenses. My current focus is on building secure micro-architectures that detect and thwart timing and power side-channel attacks. I am fortunate to have Prof. Chester and Biswa as academic collaborators in these topics of interest.
I was an integral part of the SHAKTI processor program, involved in almost all facets of the chip-design stack right from RTL design to post silicon validation of India’s very first indigenous microprocessor family called C-Class. The design was taped-out in Intel’s 22nm FFL process and SCL’s 180nm process and boots linux successfully. I am currently driving the AI/ML accelerators development in the SHAKTI group.
- Surya Selvam, Vinod Ganesan, Pratyush Kumar, “FuSeConv: Fully Separable Convolutions for Fast Inference on Systolic Arrays”, to appear in proceedings of Design, Automation & Test in Europe (DATE), 2021. (paper)
- Vishal Gupta, Vinod Ganesan, Biswabandan Panda, “Seclusive Cache Hierarchy for Mitigating Cross-Core Cache and Coherence Directory Attacks”, to appear in proceedings of Design, Automation & Test in Europe (DATE), 2021. (paper)
- Vinod Ganesan, Surya Selvam, Sanchari Sen, Pratyush Kumar, and Anand Raghunathan, “A Case for Generalizable DNN Cost Models for Mobile Devices”, in proceedings of International Symposium on Workload Characterization (IISWC), 2020. (paper) (slides)
- Vinod Ganesan, Sanchari Sen, Pratyush Kumar, Neel Gala, Kamakoti Veezhinathan and Anand Raghunathan, “Sparsity-Aware Caches to Accelerate Deep Neural Networks”, in proceedings of Design, Automation & Test in Europe (DATE), 2020. (paper)
- Muhammad Arsath, Vinod Ganesan, Rahul Bodduna and Chester Rebeiro, “PARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance”, in proceedings of International Symposium on Hardware Oriented Security and Trust (HOST), 2020. (paper) (Best paper nomination)
- Rahul Bodduna, Vinod Ganesan, Patanjali SLPSK, Kamakoti Veezhinathan and Chester Rebeiro, “BRUTUS: Refuting the Security Claims of the Cache Timing Randomization Countermeasure proposed in CEASER”, in Computer Architecture Letters (CAL), 2020. (paper)
- Delivered a talk on the 22nm SHAKTI C-Class tapeout in RISC-V Workshop
(2018) representing the SHAKTI group (link)